Phase-locked loop (PLL) circuits are frequently utilized to lock an oscillator in phase with a reference signal. PLL circuits are often utilized within receivers in digital communication systems to generate a local clock signal that is phase aligned with an incoming reference signal. The phase aligned local clock signal facilitates the receipt and processing of synchronous data sent by a transmitter in the communication system.
A conventional PLL circuit includes a phase detector, a filter and a voltage-controlled oscillator (VCO). In the conventional PLL circuit, the phase detector compares the incoming reference signal and the output of the VCO. The phase detector generates an error signal that is representative of the phase difference of the reference signal and the VCO output The error signal is filtered and applied to the control input of the VCO to produce an output signal that tracks the phase of the reference signal.
Recently, a number of receiver architectures have become popular in digital communication systems. Many receivers recover the clock from the incoming data sequence, using a PLL circuit. One or more data samplers typically sample the incoming data and an edge detector samples the incoming data signal between two adjacent bits, to identify data edges and thereby provide bit synchronization. In addition to performing bit synchronization, the receivers must also perform byte and frame alignment to extract data correctly.
Byte and frame alignment is typically implemented using error detecting codes or frame header detection. An error detecting code implementation typically encodes bytes, and then if frequent errors are detected at the receiver, assumes the data has been received properly, but that the data is not properly aligned. In a frame header detection implementation, the incoming data stream is monitored until a frame header is identified, thereby indicating byte placement. The error detector and frame header detector can be significantly simplified if bytes are already aligned at their input.